Cabanis, D., 2000. Application of object-orientation to HDL-based designs. Doctorate Thesis (Doctorate). Bournemouth University.
Full text available as:
|PDF (.pdf supplied by EThOS) - Submitted Version|
The increase in the scale of VLSI circuits over the last two decades has been of great importance to the development process. To cope with this evergrowing design complexity. new development techniques and methodologies have been researched and applied. The early 90's have witnessed the uptake of a new kind of design methodology based on Hardware Description Languages (HDL). This methodology has helped to master the possibilities inherent in our ability to manufacture ever-larger designs. However. while HDL based design methodology is sufficient to address today's standard ASIC sizes, it reaches its limits when considering tomorrow's design scales. Already. RISC processor chip descriptions can contain tens of thousands of HDLlines. Object-Oriented design methodology has recently had a considerable Impact in the software design community as it is tightly coupled with the handling of complex systems. Object-Orientation concentrates on data rather than functions since. throughout the design process. data are more stable than functions. Methodologies for both hardware and software have been introduced through the application of HDLs to hardware design. Common design constructs and principles that have proved successful in software language development should therefore be considered in order to assess their suitability for HDLs based designs. A new methodology was created to emphasise on encapsulation. abstraction and classification of designs. using standard VHDL constructs. This achieves higher levels of modelling along with an Improved reusability through design inheritance. The development of extended semantics for integrating Object-Orientation in the VHDL language is described. Comparisons are made between the modelling abilities of the proposed extension and other competing proposals. A UNIX based Object-Oriented to standard VHDL pre-processor is described along with translation techniques and their issues related to synthesis and simulation. This tool permitted validation of the new design methodology by application to existing design problems.
|Item Type:||Thesis (Doctorate)|
|Additional Information:||A thesis submitted in partial fulfilment of the requirements of Bournemouth University for the degree of Doctor of Philosophy. If you feel this work infringes your copyright please contact the BURO manager.|
|Subjects:||Technology > Engineering > Electrical and Electronic Engineering|
Generalities > Computer Science and Informatics
|Group:||Faculty of Science and Technology|
|Deposited By:||INVALID USER|
|Deposited On:||08 Nov 2006|
|Last Modified:||10 Sep 2014 15:38|
Downloads per month over past year
|Repository Staff Only -|