Design synthesis for dynamically reconfigurable logic systems.

Vasilko, M., 2000. Design synthesis for dynamically reconfigurable logic systems. PhD Thesis (PhD). Bournemouth University.

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Abstract

Dynamic reconfiguration of logic circuits has been a research problem for over four decades. While applications using logic reconfiguration in practical scenarios have been demonstrated, the design of these systems has proved to be a difficult process demanding the skills of an experienced reconfigurable logic design expert. This thesis proposes an automatic synthesis method which relieves designers of some of the difficulties associated with designing partially dynamically reconfigurable systems. A new design abstraction model for reconfigurable systems is proposed in order to support design exploration using the presented method. Given an input behavioural model, a technology server and a set of design constraints, the method will generate a reconfigurable design solution in the form of a 3D floorplan and a configuration schedule. The approach makes use of genetic algorithms. It facilitates global optimisation to accommodate multiple design objectives common in reconfigurable system design, while making realistic estimates of configuration overheads and of the potential for resource sharing between configurations. A set of custom evolutionary operators has been developed to cope with a multiple-objective search space. Furthermore, the application of a simulation technique verifying the lll results of such an automatic exploration is outlined in the thesis. The qualities of the proposed method are evaluated using a set of benchmark designs taking data from a real reconfigurable logic technology. Finally, some extensions to the proposed method and possible research directions are discussed.

Item Type:Thesis (PhD)
Additional Information:A thesis submitted in partial fulfilment of the requirements of Bournemouth University for the degree of Doctor of Philosophy. If you feel this work infringes your copyright please contact the BURO manager.
Subjects:Technology > Engineering > Electrical and Electronic Engineering
Generalities > Computer Science and Informatics > Artificial Intelligence
Generalities > Computer Science and Informatics
Group:Faculty of Science and Technology
ID Code:291
Deposited By:INVALID USER
Deposited On:07 Nov 2006
Last Modified:10 Sep 2014 15:38

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