Medhat, S. S. A., 1993. High level behavioural modelling of boundary scan architecture. PhD Thesis (PhD). Bournemouth University.
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This project involves the development of a software tool which enables the integration of the IEEE 1149.1/JTAG Boundary Scan Test Architecture automatically into an ASIC (Application Specific Integrated Circuit) design. The tool requires the original design (the ASIC) to be described in VHDL-IEEE 1076 Hardware Description Language. The tool consists of the two major elements: i) A parsing and insertion algorithm developed and implemented in 'C'; ii) A high level model of the Boundary Scan Test Architecture implemented in 'VHDL'. The parsing and insertion algorithm is developed to deal with identifying the design Input/Output (I/O) terminals, their types and the order they appear in the ASIC design. It then attaches suitable Boundary Scan Cells to each I/O, except power and ground and inserts the high level models of the full Boundary Scan Architecture into the ASIC without altering the design core structure.
|Item Type:||Thesis (PhD)|
|Additional Information:||A thesis submitted in partial fulfilment of the requirement of Bournemouth University for the degree of Doctor of Philosophy. If you feel that this work infringes your copyright please contact the BURO Manager.|
|Subjects:||Generalities > Computer Science and Informatics|
|Group:||School of Design, Engineering & Computing|
|Deposited By:||INVALID USER|
|Deposited On:||07 Nov 2006|
|Last Modified:||07 Mar 2013 14:34|
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